The present invention relates to a semiconductor memory device, and, more particularly, to a non-volatile semiconductor memory device including a flash EEPROM (Electrically Erasable and Programmable Read Only Memory).
Non-volatile semiconductor memories, such as a Ferro-electric Random Access Memory, EPROM (Erasable and Programmable Read Only Memory) and EEPROM are used in many types of electronic devices. The EPROM and EEPROM have a plurality of memory cells each including a floating gate for storing a charge and a control gate for detecting a change in the threshold voltage in accordance with the quantity of charge stored in the floating gate. One feature of the EEPROM is that the entire array of memory cells can be erased. The EEPROM includes a flash EEPROM, which has its memory cell array separated into a plurality of blocks. The flash EEPROM can selectively erase data block by block. The flash EEPROM has the following advantages:
(1) Non-volatile property for stored data; PA1 (2) Low power consumption; PA1 (3) Electrically rewritable (rewritable on board); and PA1 (4) Low cost.
Therefore, the flash EEPROM is desirable as a memory for storing programs or data in electronic devices, such as portable telephones and portable information terminals.
In general, there are two types of memory cells in a flash EEPROM: one is a split gate type and the other is a stack gate type. International Patent Publication WO92/18980 and U.S. Pat. No. 5,029,130 disclose a split gate flash EEPROM.
FIG. 1 is a cross-sectional view schematically illustrating a conventional split gate memory cell 101 disclosed in U.S. Pat. No. 5,029,130. The split gate memory cell 101 has a source S of an N-type conductivity and a drain D of the N-type conductivity, both defined on a single crystalline silicon substrate 102 having a P-type conductivity, a floating gate FG provided on a first silicon oxide film 103 over a channel CH between the source S and drain D, and a control gate CG provided on a second silicon oxide film 104 over the floating gate FG. A part of the control gate CG is arranged as a select gate 105 on the first insulator film 103 over the channel CH, and the remaining part of the control gate CG is arranged on the second insulator film 104 over the floating gate FG.
FIG. 2 is a block diagram showing a conventional flash EEPROM 121 having a plurality of split gate memory cells 101. The flash EEPROM 121 includes a memory cell array 122, a row decoder 123, a column decoder 124, an address pad 125, an address buffer 126, an address latch 127, a data pad 128, an input buffer 129, a sense amplifier group 130, an output buffer 131 and a control core circuit 132.
The memory cell array 122 has a matrix of split gate memory cells 101, a plurality of word lines WLa to WLz each commonly connected to the control gates CG of an associated row of the memory cells 101, a plurality of bit lines BLa to BLz each commonly connected to the drains D of an associated column of the memory cells 101, and a source line SL connected to the source S all of the memory cells. The source line SL is also connected to a ground.
A row address and a column address supplied from an external unit (not shown) are supplied to the address buffer 126 via the address pad 125. The address buffer 126 transfers the row address and column address to the address latch 127. The address latch 127 latches the row and column addresses and transfers the row address to the row decoder 123 and the column address to the column decoder 124. The row decoder 123 selects one word line in accordance with the row address and controls the voltage applied to the selected word line WLm in accordance with an individual operation mode (FIG. 5). The column decoder 124 selects one bit line in accordance with the column address and controls the voltage applied to the selected bit line, also in accordance with the individual operation modes.
Data supplied from the external unit (not shown) is supplied to the input buffer 129 via the data pad 128. The input buffer 129 transfers the data to the column decoder 124. The column decoder 124 controls the voltage applied to any selected one of the bit lines BLa-BLz according to the data. Data read from an arbitrary memory cell 101 is transferred from the selected bit line to the sense amplifier group 130 via the column decoder 124. The sense amplifier group 130 includes a plurality of sense amplifiers (not shown). The column decoder 124 operates so as to connect the selected bit line to the sense amplifiers. The sense amplifier group 130 discriminates the data and supplies it to the output buffer 131. The output buffer 131 supplies the data to the data pad 128. The thus read data is supplied to an external unit via the data pad 128.
The control core circuit 132 controls the operations of the row decoder 123, the column decoder 124, the address buffer 126, the address latch 127, the input buffer 129, the sense amplifier group 130 and the output buffer 131.
The individual operation modes (erase mode, write mode and read mode) of the flash EEPROM 121 will now be discussed with reference to FIG. 3. In any one of the operation modes, a voltage of the ground level is applied to the common source line SL (i.e., the source region S of all of the memory cells 101 and the substrate 102).
(a) Erase Mode
In erase mode, a voltage of the ground level (0 V) is applied to all of the bit lines BLa-BLz. A voltage of about +15 V is applied to a selected word line WLm and a voltage of the ground level is applied to the other, non-selected word lines WLa-WLl and WLn-WLz. Data is erased from all of the memory cells 101 connected to the selected word line WLm as the electric potential of the control gates CG of those memory cells 101 are pulled up to about +15 V.
When the electric potential of the control gate CG is about +15 V and the electric potential of the drain is 0 V, a high electric field is produced between the control gate CG and the floating gate FG so that a Fowler-Nordheim (FN) tunnel current flows between the floating gate FG and the control gate CG. Consequently, electrons in the floating gate FG are pulled out to the control gate CG, resulting in data erasure. The erasing operation is based on the fact that the electrostatic capacitance between the drain D and the floating gate FG is significantly greater than that between the control gate CG and the floating gate FG. Simultaneous selection of a plurality of word lines WLa-WLz allows for data erasure of all of the memory cells 101 connected to the selected individual word lines. Such an erasure is called "block erasure".
(b) Write Mode
In write mode, a voltage of about +1 V is applied to a selected word line WLm, and a voltage of the ground level is applied to the other, non-selected word lines WLa-WLl and WLn-WLz. A voltage of about +12 V is applied to a selected bit line BLm, and a voltage of ground level is applied to the other, non-selected bit lines BLa-BLl and BLn-BLz. Consequently, the electric potential of the floating gate FG is pulled up by the capacitive coupling between the source S and the floating gate FG, thus producing a high electric field between the control gate CG and the floating gate FG. Thus, the electrons in the channel CH are accelerated to become hot electrons which are supplied to the floating gate FG. As a result, a charge is stored in the floating gate FG of the selected memory cell 101 and 1-bit of data is written.
It is noted that each memory cell 101 has a threshold voltage Vth of +0.5 V and includes a transistor, which includes a control gate CG, source S and drain D. Therefore, electrons in the source S are moved in the channel CH in the weakly inverted state from P to N, so that the cell current flows to the drain D from the source S.
(c) Read Mode
In read mode, a voltage of about +4 V is applied to a selected word line WLm, and the voltage of the ground level is applied to the other, non-selected word lines WLa-WLl and WLn-WLz. A voltage of about +3 V is applied to a selected bit line BLm and the voltage of the ground level is applied to the other, non-selected bit lines BLa-BLl and BLn-BLz. As a result, the cell current which flows to the source S of the memory cell 101 in the erased state from the drain D becomes greater than the cell current flowing in the memory cell 101 in the write state. This is because the channel CH directly below the floating gate FG of the data-erased memory cell is enabled, while the channel CH directly below the floating gate FG of the data-written memory cell is disabled in the memory cell in the write state.
More specifically, because electrons are drained from the floating gate FG of a data-erased memory cell, the floating gate FG is positively charged. Therefore, the channel CH or the memory cell is enabled so that a current flows. As electrons are supplied into the floating gate FG of a data-written memory cell, the floating gate FG is negatively charged. The channel CH or memory cell is thus disabled so that a current does not flow. A NMOS split gate type memory cell is used as the memory cell 101. A PMOS split gate type memory cell may be used as the memory cell 101. In this case, the channel CH or memory cell is disabled so that a current does not flow when the floating gate FG has a high electric potential, and the channel CH or the memory cell is enabled so that a current flows when the floating gate FG has a low electric potential.
Each sense amplifier in the sense amplifier group 130 discriminates the level of the cell current flowing in the associated memory cell as erase data "1" or write data "0". In this manner, binary data having a data value "1" indicating the erased state and a data value "0" indicating the written state may be stored in each memory cell.
International Patent Publication WO92/18980 discloses a flash EEPROM in which the source S of the split gate memory cell 101 is identified as a "drain" and the drain D is identified as a "source". FIG. 4 shows voltages applied to a selected word line, a selected bit line, the common source line and the substrate in the individual operation modes of this flash EEPROM.
In the above two types of flash EEPROMs, multi-value data can be stored in any memory cell 101 by adjusting the value of the cell current Id which flows in the memory cell. As shown in FIG. 5, the electric potential Vfg of the floating gate FG (hereinafter referred to as "floating gate potential") is the electric potential of the floating gate FG with respect to the electric potential of the source S, and is given by the following equation: EQU Vfg=Vfgw+Vfgc
where Vfgw is the electric potential produced by a charge stored in the floating gate FG in write mode and Vfgc is the potential produced by the capacitive coupling with the drain D. In read mode, the electric potential Vfgc is constant so that the cell current value Id is specifically determined by the electric potential Vfgw. In write mode, the amount of charge in the floating gate FG or the electric potential Vfgw is controlled by adjusting the write operation time. The control on the floating gate potential Vfg permits the cell current value Id in read mode to be set at an arbitrary value.
Suppose that a data value "00" is associated with a cell current value Id which is less than 20 .mu.A, a data value "01" is associated with a cell current value Id which is equal to or greater than 20 .mu.A and less than 50 .mu.A, a data value "10" is associated with a cell current value Id which is equal to or greater than 50 .mu.A and less than 80 .mu.A, and a data value "11" is associated with a cell current value Id which is equal to or greater than 80 .mu.A. In this case, the write operation time is controlled so that individual floating gate potentials Va, Vb and Vc corresponding to the individual cell current values Id (20 .mu.A, 50 .mu.A and 80 .mu.A) are acquired in write mode. In this manner, four-value (2-bit) data is stored in a single memory cell.
In read mode, when the floating gate potential Vfg is smaller than the threshold voltage Vth (+0.5 V), the cell current value Id is 0. When the floating gate potential Vfg exceeds the threshold voltage Vth, the cell current value Id increases. When the floating gate potential Vfg exceeds +3.5 V, the cell current value Id is saturated due to the constant resistance of the channel CH which lies directly below the control gate CG. That is, the channel CH serves as a constant resistor because a constant voltage (+4 V) is applied to the control gate CG. Therefore, a series connection of the transistor to the constant resistor of the channel CH is present in the memory cell. When the floating gate potential Vfg is less than a given value (+3.5 V), as apparent from the above, the cell current value Id varies in accordance with the characteristic of the transistor.
To ensure that data is written accurately, it is important to precisely control the floating gate voltage of each memory cell in the write mode. In other words, it is important to control the voltage applied to the floating gate to high precision to ensure that the floating gate will have a desired electric potential after a write operation.
Japanese Unexamined Patent Publication No. 4-57294 discloses a write verification technique for multi-value storage modes to ensure high-precision control of the floating gate voltage. The write verification technique first performs writing to memory cells for a given time (e.g., several hundred nanoseconds to several microseconds), and then performs a verify read operation. Then, the data value to be written is compared with the data value that has been read. When the data values do not match, writing is once again executed for a given time. In this manner, the write operation, the verify read operation and the comparison are repeated until the read and write data values coincide. The write verification method is however disadvantageous for fast data writing for at least the following reasons.
(1) It takes time to perform verify read operations and comparison operations, and such operations do not directly contribute to writing data in memory cells. More specifically, the transition from the write mode to the verify read mode requires a predetermined time (e.g., several microseconds) to switch from the write bias conditions to the appropriate read bias conditions. In addition, a total of approximately 100 to 300 nsec are needed for the verify read operation and the comparing operation.
(2) To control the electric potential of the floating gate more precisely, the number of repetitions of a cycle (i.e., the write operation, verify read operation and comparing operation) is increased, thus unfortunately increasing the overall time needed for the write operation. Higher precision control is achieved by suppressing the amount of a change in the electric potential of the floating gate in a single write operation. It is thus necessary to repeat the cycle while shortening the time needed for a single write operation.
(3) Since the timing control for switching the individual operations in the cycle from one to another is delicate and complex, a semiconductor memory device control circuit is complex and chip area therefore is increased.
The present invention relates to a semiconductor memory device which writes data in memory cells very fast while precisely controlling data writing in the memory cells.